Information processing devices including image processors generally use large-volume and low-cost DRAMs to store a large amount of data. More particularly, recent image processors require DRAMs with not just memory capacity but with high data transferring capability (hereinafter referred to as a memory bandwidth) for High Definition (HD) image processing in MPEG 2 and H.264, simultaneous multiple channel processing, and high-quality 3D graphics processing.
For achieving the high memory bandwidth, some conventional methods have been generally known, including: (1) improving the operational frequency of bus; (2) allowing a wide bus width in a memory; and a method with the combination of (1) and (2).
On the other hand, when accessing a DRAM, it is generally necessary to designate a bank and a row to be accessed and activate the bank and the row in advance. In addition, when changing the row to be accessed in the same bank, it is necessary to precharge the accessed row first, and activate the row to be newly accessed. During the activation process and the precharge process, the bank cannot be accessed, which generates an inaccessible period when switching the row in the same bank and generates latency in data bus. In order to make up for the disadvantage, in the regular DRAM access control, a control called bank interleaving is performed which masks the inaccessible period by activating and precharging another bank while transferring the data to a certain bank. The bank interleave control allows constant data transfer on the data bus in appearance during the data transfer to the bank. It is necessary that the data transfer time to the other bank exceeds the inaccessible period so that the bank interleaving is effective.
However, in the cases of both (1) and (2) for achieving high memory bandwidth, data transfer amount per unit time increases. Meanwhile, the absolute time of the inaccessible period does not change, and thus the data transfer amount necessary for masking the inaccessible period increases. As a result, even with the bank interleaving, the inaccessible period is not fully masked unless the data transfer amount to the other bank is increased, more specifically, unless the transfer size per access is increased. Consequently, latency in the data bus is generated, and the access efficiency is reduced. This indicates significant reduction in the access efficiency in a system where frequent access with small transfer size is performed.
Patent Reference 1 discloses a conventional method to solve the problem. FIG. 31 shows a circuit configuration of the conventional method. With this, method, access efficiency of bus is improved by masking the inaccessible period generated in one device with the data transfer time of the other device by alternate time-division access of the memory devices 0 and 1 at a predetermined timing in the command generating unit based on the signals from the counters 0 and 1. With this control, in the cases of both (1) and (2) for achieving high memory bandwidth, the inaccessible period which could not be masked by the bank interleaving in the same device can be masked by the access to the other device, and thus it is possible to prevent the access efficiency from being decreased without increasing the transfer size per access. This indicates that it is possible to limit the reduction in the access efficiency in a system where frequent access with small transfer size is performed.    [Patent Reference 1] Japanese Unexamined Patent Application Publication No. 9-190376